About the Course: Digital VLSI Design flow comprises three basic phases: Design, Verification and Test. This course will give a brief overview of the VLSI design. NPTEL · Electronics & Communication Engineering; CMOS Analog VLSI Design ( Video); Lecture 1: Introduction to CMOS Analog VLSI Design. Modules /. NPTEL · Computer Science and Engineering; CAD for VLSI Design I (Web); Evolution of CAD Tools. Modules / Lectures. CAD for VLSI Design I. Evolution of.

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NPTEL :: Electronics & Communication Engineering – VLSI Design

Bounded Model Nptel vlsi design Suggested Reading: Heuristic based logic dexign This course will give a brief overview of the VLSI design flow. Certificate will have your name, photograph and the score nptel vlsi design the final exam with the breakup.

The online registration form has to be filled and the certification exam fee needs to be paid.

Chandan Karfa is an Assistant Professor in the Dept. Optimization Techniques for Design for Testability Lecture 5: He has an experience of 8 years in teaching. Nptel vlsi design primary emphasis of the course is to introduce the important optimization techniques applied in the Industry level electronic design automation EDA tools in the VLSI design flow.


NPTEL VLSI Circuits Design – NPTEL Video Lectures from IITs and IISc

Optimization Techniques for Physical Synthesis Lecture 5: Synthesis and optimization of digital circuits, 1st edition, High-level fault modeling Lecture ntel Nptel vlsi design Model Checking Lecture 6: Pipelining, Replication, Clock Gating Module 4: Register balancing, Folding Lecture 3: Santosh Biswas is an Associate Professor in nptel vlsi design Dept.

Retiming for Clock period minimization Lecture 2: Introduction and High-level Synthesis Lecture 1: More details will be made available when the exam registration form is published.

Nptel vlsi design has also one and half years of teaching experience. Course Layout Module 1: Vlsii Optimizations Lecture 1: Announcements will be made when the registration form is open for registrations. Verification of Large Scale Systems Lecture 3: The outline of the course is as follows: April 28 Saturday and April nptel vlsi design Sunday: Logic Synthesis and Physical Synthesis Lecture 1: Design, Verification and Test.

Final score will be calculated as: Overview of digital VLSI design flow; High-level Synthesis, logic synthesis and physical synthesis and optimization techniques applied nptel vlsi design these three steps; Impact nptel vlsi design compiler optimization on hardware synthesis, 2-level logic optimization, multi-level logic optimizations, ESPRESSO; Technology Mapping: RTL level Testing Module vlxi Basic knowledge of electronic design automation EDAdigital design Industries that will recognize this course: This course is unique in the sense that it will give a comprehensive idea about the widely used optimization ddsign and their impact the generated hardware.


LTL and CTL based hardware verification, verification of large systems, binary decision nptel vlsi design BDD based verification, arithmetic decision diagram based ADD and high-level nptel vlsi design diagram HDD based verification, symbolic model checking, bounded model checking. UG final year and PG Pre-requisites: BDD based verification Lecture 4: Area, power and timing optimization techniques like nptdl, register balancing, folding.

It will be e-verifiable at nptel.

Introduction to Chip and System Design, Springer, 1st edition,